PIC16C924-04/L【PDF 36/115 页】IC MCU OTP 4KX14 LCD DVR 68PLCC

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Sheet目录3832

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1997 Microchip Technology Inc.

DS30444E - page 27

PIC16C9XX

4.2.2.5

PIR1 REGISTER

This register contains the individual ag bits for the

peripheral interrupts.

Note:

Interrupt ag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt ag bits are clear prior to enabling an

interrupt.

FIGURE 4-7:

PIR1 REGISTER (ADDRESS 0Ch)

R/W-0

U-0

R/W-0

LCDIF

ADIF(1)

—

SSPIF

CCP1IF

TMR2IF

TMR1IF

= Readable bit

W = Writable bit

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

LCDIF: LCD Interrupt Flag bit

1 = LCD interrupt occurred (must be cleared in software)

0 = LCD interrupt did not occur

bit 6:

ADIF: A/D Converter Interrupt Flag bit(1)

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete

bit 5-4: Unimplemented: Read as '0'

bit 3:

SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit 2:

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1:

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0:

TMR1IF: TMR1 Overow Interrupt Flag bit

1 = TMR1 register overowed (must be cleared in software)

0 = TMR1 register did not overow

Note 1: Bit ADIF is reserved on the PIC16C923, always maintain this bit clear.

Interrupt ag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ag bits are clear prior to

enabling an interrupt.

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